Increasing complexity of integrated circuits has generally forced the industry to abandon partial scan, which can remove scan multiplexers corresponding to some of the flip-flops, disconnecting them from the scan path. As a result, controllability and observability of these flip-flops can be compromised, typically necessitating sequential Automatic Test Pattern Generation (ATPG), where these flip-flops can be controlled and observed through functional paths. The computational cost of sequential ATPG typically cannot be afforded, given the complexity of integrated circuits today. Consequently, the industry has generally given up on partial scan, and adopted full scan despite its costs.
Full scan typically incurs area, performance and test costs. An insertion of as many multiplexers as the number of flip-flops in the design can impose a considerable area cost. Furthermore, these multiplexers are typically inserted on functional paths, resulting in critical path prolongation by a multiplexer delay, and hence degrading the performance of the design timing-wise. Full scan can also incur significant test costs. Every test pattern can include as many bits as the number of flip-flops in the design, translating into high test time and test data volume. Another problem that full scan imposes can be the excessive switching activity during test, as all the flip-flops are active during shift operations. Elevated levels of power dissipation (see, e.g., P. Girard, “Survey of low-power testing of VLSI circuits,” IEEE Design Test of Computers, vol. 19, no. 3, pp. 80-90, May 2002) occur during testing, which, if overlooked, can cause reliability issues.
A computationally efficient partial scan can be a remedy of the problems of full scan (see, e.g., J. Rearick, “The case for partial scan,” International Test Conference, p. 1032, November 1997). Removal of scan multiplexers, and thus taking some of the flip-flops off the scan path can:                Reduce area cost.        Potentially improve the critical paths of the design, and thus, can enhance functional performance.        Reduce the scan path length, and thus, can decrease test time and test data volume. It can be a form of test data compression.        Reduce switching activity during testing and can leash power dissipation and IR drop, as only the scan flip-flops typically toggle during shift operations while the non-scan flip-flops can be inactive during shift.        
Research has also been conducted in partial scan design. The previously proposed techniques in this field can be classified mainly into three categories: (a) structure-based techniques that typically involves breaking the cycles and/or reducing scan depth (see, e.g., P. Ashar and S. Malik, “Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications,” Design Automation Conference, pp. 77-80, June 1994; S. T. Chakradhar, A. Balakrishnan, and V. D. Agrawal, “An exact algorithm for selecting partial scan flip-flops,” Design Automation Conference, pp. 81-86, June 1994; K.-T. Cheng and V. D. Agrawal, “A partial scan method for sequential circuits with feedback,” IEEE Transactions on Computers, vol. 39, no. 4, pp. 544-548, April 1990; K.-T. Cheng, “Single clock partial scan,” IEEE Design Test of Computers, vol. 12, no. 2, pp. 24-31, 1995; V. Chickermane and J. H. Patel, “An optimization based approach to the partial scan design problem,” International Test Conference, pp. 377-386, September 1990; V. Chickermane and J. H. Patel, “A fault oriented partial scan design approach,” International Conference on Computer-Aided Design, pp. 400-403, November 1991; R. Gupta and M. A. Breuer, “The ballast methodology for structured partial scan design,” IEEE Transactions on Computers, vol. 39, no. 4, pp. 538-544, April 1990; A. Kunzmann and H. J. Wunderlich, “An analytical approach to the partial scan design problem,” Journal of Electronic Testing: Theory and Applications, vol. 1, pp. 163-174, 1990; D. H. Lee and S. M. Reddy, “On determining scan flip-flops in partial-scan designs,” International Conference on Computer-Aided Design, pp. 322-325, November 1990; J. Park, S. Shin, and S. Park, “A partial scan design by unifying structural analysis and testabilities,” International Symposium on Circuits and Systems, vol. 1, pp. 88-91, 2000; and S.-E. Tai and D. Bhattacharya, “A three-stage partial scan design method using the sequential circuit flow graph,” International Conference on VLSI Design, pp. 101-106, January 1994), (b) testability-based techniques that select scan flip-flops based on testability improvements (see, e.g., V. Chickermane and J. H. Patel, “An optimization based approach to the partial scan design problem,” International Test Conference, pp. 377-386, September 1990; V. Chickermane and J. H. Patel, “A fault oriented partial scan design approach,” International Conference on Computer-Aided Design, pp. 400-403, November 1991; M. Abramovici, J. J. Kulikowski, and R. K. Roy, “The best flip-flops to scan,” International Test Conference, p. 166, October 1991; V. Boppana and W. K. Fuchs, “Partial scan design based on state transition modeling,” International Test Conference, pp. 538-547, October 1996; P. Kalla and M. Ciesielski, “A comprehensive approach to the partial scan problem using implicit state enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 810-826, July 2002; K. S. Kim and C. R. Kime, “Partial scan by use of empirical testability,” International Conference on Computer-Aided Design, pp. 314-317, November 1990; P. S. Parihk and M. Abramovici, “Testability-based partial scan analysis,” Journal of Electronic Testing: Theory and Applications, vol. 7, pp. 47-60, August 1995; G. S. Saund, M. S. Hsiao, and J. H. Patel, “Partial scan beyond cycle cutting,” International Symposium on Fault-Tolerant Computing, pp. 320-328, June 1997; E. Trischler, “Incomplete scan path with an automatic test generation methodology,” International Test Conference, pp. 153-162, 1980; D. Xiang, S. Venkataraman, W. K. Fuchs, and J. H. Patel, “Partial scan design based on circuit state information,” Design Automation Conference, pp. 807-812, June 1996; D. Xiang and J. H. Patel, “A global algorithm for the partial scan design problem using circuit state information,” International Test Conference, pp. 548-557, October 1996; and D. Xiang and J. H. Patel, “Partial scan design based on circuit state information and functional analysis,” IEEE Transactions on Computers, vol. 53, no. 3, pp. 276-287, March 2004), and (c) test generation-based techniques which intertwine test generation and scan flip-flop selection (see, e.g., V. D. Agrawal, K.-T. Cheng, D. D. Johnson, and T. S. Lin, “Designing circuits with partial scan,” IEEE Design Test of Computers, vol. 5, no. 2, pp. 8-15, April 1988; M. S. Hsiao, G. S. Saund, E. M. Rudnick, and J. H. Patel, “Partial scan selection based on dynamic reachability and observability information,” International Conference on VLSI Design, pp. 174-180, January 1998; H.-C. Liang and C. L. Lee, “An effective methodology for mixed scan and reset design based on test generation and structure of sequential circuits,” Asian Test Symposium, pp. 173-178, 1999; X. Lin, I. Pomeranz, and S. M. Reddy, “Full scan fault coverage with partial scan,” Design, Automation and Test in Europe, pp. 468-472, 1999; I. Park, D. S. Ha, and G. Sim, “A new method for partial scan design based on propagation and justification requirements of faults,” International Test Conference, pp. 413-422, October 1995; and S. Sharma and M. S. Hsiao, “Combination of structural and state analysis for partial scan,” International Conference on VLSI Design, pp. 134-139, 2001). Other partial scan techniques can include those driven by layout constraints (see, e.g., V. Chickermane and J. H. Patel, “An optimization based approach to the partial scan design problem,” International Test Conference, pp. 377-386, September 1990), timing constraints (see, e.g., J.-Y. Jou and K.-T. Cheng, “Timing-driven partial scan,” International Conference on Computer-Aided Design, pp. 404-407, November 1991), re-timing (see, e.g., S. T. Chakradhar, A. Balakrishnan, and V. D. Agrawal, “An exact algorithm for selecting partial scan flip-flops,” Design Automation Conference, pp. 81-86, June 1994 and D. Kagaris and S. Tragoudas, “Retiming-based partial scan,” IEEE Transactions on Computers, vol. 45, no. 1, pp. 74-87, January 1996), and toggling rate of flip-flops and entropy measures (see, e.g., O. Khan, M. L. Bushnell, S. K. Devanathan, and V. D. Agrawal, “Spartan: A spectral and information theoretic approach to partial scan,” International Test Conference, p. Paper 21.1, 2007). These techniques typically necessitate the utilization of sequential ATPG or combinational ATPG with time frame expansion to generate test patterns on the partially scanned design, not only failing to comply with the existing design/test flow that industry utilizes today but also typically incapable of ensuring the quality of full scan.